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IC Packaging

Think miniaturization, think iNPACK™

IC Capabilities

We provide IC packages in a complex array of shapes, sizes, and materials, giving you the ability to select the exact features and functionality best suited to your specific application. This determination however is dependent upon a number of factors, including: Pitch, Dimensions, Lead Count, Thermal Requirements and Costing.

QFN (Quad Flat No Lead), represents a specific IC Packaging solution. iNPACK offers a customized panel-level solution featuring a plastic-encapsulated laminate panel, with a variety of dielectric and CTE options for electrical interconnection with the PCB. This type of packaging can be offered as a full turn-key solution, (including assembly and testing), or as a stand-alone substrate, combined with cavity lid.

Process & Machinery

SMT P&P

Curing (Flux-less Vacuum Soldering)

Laser Marketing / Labeling / Print

Reflow

Wedge & Ball

Dicing (Package Sawing)

XRAY

Plasma

Cross Section

Die Attach (soldering and adhesive)

Molding (Encapsulation)

QFN Package

Sintering

Through Mold Interconnection

Dispensing & Stamping

Laser Jet Ball (for BGA)

Laminate QFN Package Types

Dimensions

Pitch

Leads number

Leads number

Lid style

3x3

0.5/0.65

16

12

organic/ceramic/glass/metal/molded

4x4

0.5/0.65

20

16

organic/ceramic/glass/metal/molded

5x5

0.5/0.65

32

24

organic/ceramic/glass/metal/molded

7x7

0.5/0.65

48

36

organic/ceramic/glass/metal/molded

8x8

0.5/0.65

56

44

organic/ceramic/glass/metal/molded

10x10

0.5/0.65

72

56

organic/ceramic/glass/metal/molded

12x12

0.5/0.65

88

68

organic/ceramic/glass/metal/molded

20x20

0.5/0.65

152

116

organic/ceramic/glass/metal/molded

customized

customized

organic/ceramic/glass/metal/molded

General Features

Low profile: 0.9mm for QFN (molded)

Double-staggered lead configuration is an option

Enhanced thermal and electrical performance options available

Cost-effective panel production

ENEPIG and ENIG surface finishes

3x3 to 20x20mm body sizes

0.5 to 260 lead count available

Full in-house design capabilities

JEDEC standard outlines option

Near-hermetic sealing

3D CAD file upon request

Advantages

Material CTE Analysis

to verify that all materials used in the design of interconnections, substrates and thermal interfaces are certified to match the semiconductor properties.

Fanning Out the I/Os

from 2 or more dies to the substrate, which enables chips with improved performance and more I/Os.

Warpage Inspection

for substrate processes in micro assemblies and post SMT processes. Warpage poses a major risk on front and back-end processes, such as ball shooting, mounting, molding and interconnections.

Interconnect Options

are a critical part of packaging. We offer a wide variety of chip interconnect methodologies used in IC package design with an eye towards continuously improved technologies.

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